The present invention relates generally to SONET multiplexed communications systems, and more specifically to a SONET multiplexed communications system in which a single clock is employed to clock a single pointer generator to generate pointers for a plurality of outgoing SONET lines.
Synchronous Optical NETwork (SONET) multiplexed communications systems are known that employ time division multiplex switching techniques to route digital information between a plurality of incoming SONET lines and a plurality of outgoing SONET lines. A conventional SONET multiplexed communications system includes a plurality of incoming SONET lines, a plurality of outgoing SONET lines, and a Time Slot Interchanger (TSI) disposed between the incoming SONET lines and the outgoing SONET lines. The TSI is configured to receive digital information contained in respective time slots from the plurality of incoming SONET lines, temporarily store the digital information received during each time slot, and re-transmit that information during another time slot associated with at least one outgoing SONET line. In this way, the TSI operates as a cross-switch to route digital information from an incoming SONET line associated with a first time slot to at least one outgoing SONET line associated with a second time slot.
In the conventional SONET multiplexed system, the plurality of incoming SONET lines are clocked by respective incoming line clocks, the plurality of outgoing SONET lines are clocked by respective outgoing line clocks, and the TSI is clocked by a system clock. Because the clock rates of the incoming line clocks and the system clock may be different, respective pointer processors are typically disposed in the incoming SONET lines to compensate for timing differences between the incoming line clocks and the system clock. Similarly, because the clock rates of the system clock and the outgoing line clocks may be different, respective pointer processors are typically disposed in the outgoing SONET lines to compensate for timing differences between the system clock and the outgoing line clocks.
One drawback of the conventional SONET multiplexed communications system is that significant portions of the system are clocked at different clock rates. Specifically, significant portions of the incoming pointer processors are clocked at the incoming line clock rates while remaining portions of these pointer processors are clocked at the system clock rate. Similarly, significant portions of the outgoing pointer processors are clocked at the outgoing line clock rates while remaining portions of these pointer processors are clocked at the system clock rate. Further, the TSI is typically clocked only at the system clock rate.
Requiring significant portions of the conventional SONET multiplexed communications system to be clocked at different clock rates can make it harder to share processing resources in the communications system. Such sharing of processing resources may take place, e.g., when processing multiple combinations of concatenated SONET frame formats and/or multiple combinations of SONET bandwidths on outgoing SONET lines. Clocking significant portions of the SONET multiplexed communications system at different clock rates can also increase system complexity, which can be problematic for systems implemented on integrated circuits. This is because increased system complexity often leads to increased die sizes, which can reduce yields and increase manufacturing costs.
It would therefore be desirable to have a SONET multiplexed communications system that facilitates the sharing of processing resources while reducing overall system complexity. Such a SONET multiplexed communications system would more easily handle the generation of pointers for a plurality of outgoing SONET lines, and allow increased integration to improve yields and reduce manufacturing costs.